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8 Mbit LPC Flash
A Microchip Technology Company
CE#
LCLK
LFRAME#
SST49LF080A
Data Sheet
1st Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
1010b
1010b
1111b
Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address YYYY 5555H in 8 Clocks
Load Data AAH in 2 Clocks 2 Clocks
1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CE#
LCLK
LFRAME#
2nd Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0010b
1010b
1010b
1010b
0101b
0101b
1111b
Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address YYYY 2AAAH in 8 Clocks
Load Data 55H in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CE#
LCLK
LFRAME#
3rd Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
0000b
1000b
1111b Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address YYYY 5555H in 8 Clocks
Load Data 80H in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CE#
LCLK
LFRAME#
4th Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0101b
0101b
0101b
0101b
1010b
1010b
1111b
Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address YYYY 5555H in 8 Clocks
Load Data AAH in 2 Clocks 2 Clocks
1 Clock
1 Clock
Write the 4th command to the device in LPC mode.
CE#
LCLK
LFRAME#
5th
Memory
Write
Cycle
Address1
Data
TAR
Sync
Start next
Command
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
0010b
1010b
1010b
1010b
0101b
0101b
1111b
Tri-State
0000b
TAR
1 Clock 1 Clock
Load Address YYYY 2AAAH in 8 Clocks
Load Data 55H in 2 Clocks
2 Clocks
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CE#
LCLK
Internal
erase start
LFRAME#
6th Start
Memory
Write
Cycle
Address1
Data
TAR
Sync
Internal
erase start
LAD[3:0]
0000b
011Xb
A[31:28] A[27:24] A[23:20] A[19:16]
BAX
XXXXb
XXXXb
XXXXb
0000b
0101b
1111b
Tri-State 0000b
TAR
1 Clock 1 Clock
Load Block Address in 8 Clocks
Load Data “50” in 2 Clocks
2 Clocks
1 Clock
Write the 6th command (target sector to be erased) to the device in LPC mode.
BAX = Block Address
Note: 1. Address must be within memory address range specified in Table 4.
Figure 11: Block-Erase Command Sequence (LPC Mode)
1235 F10.0
?2011 Silicon Storage Technology, Inc.
25
DS25086A
11/11
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